发明名称 Method of reducing mechanical stress on a semiconductor die during fabrication
摘要 A method of reducing mechanical stress on an integrated circuit is disclosed including applying solder columns to the substrate for adding structural support to the package during the fabrication process.
申请公布号 US2007254407(A1) 申请公布日期 2007.11.01
申请号 US20060414780 申请日期 2006.04.28
申请人 CHIU CHIN-TIEN;TAKIAR HEM;LIU HUI;JAVA ZHU JIANG H;CHANG-CHIEN JACK;YU CHEEMEN 发明人 CHIU CHIN-TIEN;TAKIAR HEM;LIU HUI;JAVA ZHU JIANG H.;CHANG-CHIEN JACK;YU CHEEMEN
分类号 H01L21/00 主分类号 H01L21/00
代理机构 代理人
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