发明名称 LIMITER CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a limiter circuit which is capable of limiting a voltage of an analog signal and has errors of an output voltage suppressed. <P>SOLUTION: In a limiter circuit 10, an input voltage V<SB>IN</SB>is taken as a reverse phase input of a differential amplifier circuit 5, and an output of the differential amplifier circuit 5 is connected to a gate of a transistor MP1, and a drain of the transistor MP 1 is connected to a drain of another transistor M1, and a source of the transistor M1 is connected to one end of a constant current source 4 and is taken as an in-phase input of the differential amplifier circuit 5, and the differential amplifier circuit 5 and transistors MP1 and M1 constitute a feedback line, and a voltage of the source of the transistor M1 is taken as an output voltage V<SB>OUT</SB>of the limiter circuit 10. A fixed voltage VL is applied to a gate of the transistor M1 included in the feedback line, by a voltage source 6. When the input voltage V<SB>IN</SB>exceeds a voltage VL-VT1 wherein VT1 is a threshold voltage of the transistor M1, the transistor M1 is turned off to cut off the feedback line, and the output voltage V<SB>OUT</SB>is limited to VL-VT1. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007288392(A) 申请公布日期 2007.11.01
申请号 JP20060111627 申请日期 2006.04.14
申请人 NEC ELECTRONICS CORP 发明人 OGAWA HAYATO
分类号 H03G11/00 主分类号 H03G11/00
代理机构 代理人
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