发明名称 RISC TYPE CPU, COMPILER, AND MICROCOMPUTER
摘要 PROBLEM TO BE SOLVED: To provide a RISC type CPU which does not need to output unnecessary instructions into an object program in order to execute delay branch processing. SOLUTION: Since a CPU determines whether or not program branch is performed in accordance with delay option set in a branch instruction, it can determine that the delay branch is not performed with respect to the instruction at a stage that the branch instruction and the like are decoded, and in such a case a nop instruction does not need to be placed next to the branch instruction. Thus, the size of object code can be made smaller. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007287186(A) 申请公布日期 2007.11.01
申请号 JP20070207930 申请日期 2007.08.09
申请人 DENSO CORP 发明人 KAMIYA MASAHIRO;TEJIMA YOSHINORI;ISHIHARA HIDEAKI
分类号 G06F9/38;G06F9/45 主分类号 G06F9/38
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