| 发明名称 |
Semiconductor device and semiconductor device layout designing method |
| 摘要 |
In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
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| 申请公布号 |
US2007252258(A1) |
申请公布日期 |
2007.11.01 |
| 申请号 |
US20070790736 |
申请日期 |
2007.04.27 |
| 申请人 |
SHIMADA JUNICHI;KIMURA FUMIHIRO;MATSUMURA YOICHI;OHASHI TAKAKO;IWAUCHI NOBUYUKI;FUJINO TAKEYA;ARAKI TAKAYUKI;HASHIMOTO YUKIJI;YASUI TAKUYA;TAGUCHI HIROFUMI |
发明人 |
SHIMADA JUNICHI;KIMURA FUMIHIRO;MATSUMURA YOICHI;OHASHI TAKAKO;IWAUCHI NOBUYUKI;FUJINO TAKEYA;ARAKI TAKAYUKI;HASHIMOTO YUKIJI;YASUI TAKUYA;TAGUCHI HIROFUMI |
| 分类号 |
H01L23/02;G08B13/14;H01Q9/04 |
主分类号 |
H01L23/02 |
| 代理机构 |
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