发明名称 PLL CIRCUIT, METHOD FOR PREVENTING INTERFERENCE BETWEEN PLL CIRCUITS, AND OPTICAL DISK APPARATUS COMPRISING THE PLL CIRCUIT
摘要 Interference between each other PLL circuits is suppressed. Detector 30 detects whether or not the difference between output signal frequency of PLL circuit 20 having frequency of an input signal swept and a predetermined frequency is not more than first threshold value. Frequency division ratio setting circuit 40 controls to change output signal frequency of a PLL circuit 10 when the difference is not more than the first threshold value. The predetermined frequency is fixed according to output signal frequency of PLL circuit 10 . PLL circuit 10 comprises frequency dividers 11, 16 , and 17 determining output signal frequency of the PLL circuit 10 , and the frequency division ratio of frequency dividers can be changed under control of frequency division ratio setting circuit 40 . The frequency division ratio of frequency dividers is determined so that difference between output signal frequency changed by the frequency division ratio setting circuit 40 and original output signal frequency (before change) is not more than a second threshold value.
申请公布号 US2007254600(A1) 申请公布日期 2007.11.01
申请号 US20070738931 申请日期 2007.04.23
申请人 NEC ELECTRONICS CORPORATION 发明人 ISHII AKINO
分类号 H04B1/40;H04B1/06;H04B7/00 主分类号 H04B1/40
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