| 摘要 |
Circuitry includes a multiplexer to output first data and second data in response to a clock signal, the clock signal having rising and falling clock edges, where the multiplexer outputs first data at a rising clock edge and outputs second data at a falling clock edge. The circuitry includes a DAC to receive the first data and the second data and to generate, therefrom, complementary first and second signals, a filter to filter the complementary first signals and second signals and thereby produce first and second filtered signals, and a voltmeter to measure a difference between the first and second filtered signals, the difference corresponding to a duty cycle error in the clock signal. |
