Integrated semiconductor memory e.g. dynamic RAM, has memory cells attached between ends of bitline, circuit unit with control input for supplying control signal, and controllable switch connected between ends

摘要

The memory has two bit lines (BL1, BLC), where each line has two ends (11, 12, 21, 22), and a voltage generating circuit (SA) with two connectors (31, 32) at which line potentials are generated. The connectors are coupled with the ends (11, 12), and a set of memory cells (MC, MC2, MCN) is attached between the end (11) and the end (12). A circuit unit (PR) has a control input (EQL) for supplying a control signal, and a controllable switch (100) such as field effect transistor, is connected between the ends (12, 22), where a control port of the switch is coupled with the control input. An independent claim is also included for a method for testing an integrated semiconductor memory.