发明名称 |
PARALLEL INTERLEAVER, PARALLEL DEINTERLEAVER, AND INTERLEAVE METHOD |
摘要 |
<p>There is provided a parallel interleaver having a comparatively simple structure and capable of flexibly coping with modification of an interleave pattern and preventing memory access concurrence. The parallel interleaver includes a memory (702) formed by a plurality of memory banks (RAM0 to RAM4), each of which is correlated to one or more row numbers in the two-dimensional arrangement, a pattern generation unit (710) for generating a plurality of in-row rearrangement patterns defined by other row in the data structure of two-dimensional arrangement, and read-out control units (706 to 712) having a pattern generation unit (710) inside for generating a plurality of addresses according to the plurality of in-row rearrangement patterns, so that a plurality of data are simultaneously read out from the memory (702).</p> |
申请公布号 |
EP1850486(A1) |
申请公布日期 |
2007.10.31 |
申请号 |
EP20060713007 |
申请日期 |
2006.02.03 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
MOTOZUKA, HIROYUKI |
分类号 |
H03M13/27;G06F12/02;G06F12/06;H04L1/00 |
主分类号 |
H03M13/27 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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