| 摘要 |
A refresh control circuit of a semiconductor memory device is provided to reduce current consumption by omitting refresh as to an address not requiring refresh. A command decoder(110) generates an auto refresh signal by decoding a plurality of control signals. A row address control part(130) receives the auto refresh signal and an internal address signal obtained by buffering an external address signal, and generates a refresh target address in response to the input of the auto refresh signal, and generates an internal refresh active signal disabled when the refresh target address coincides with the internal address signal performing an active operation before a refresh period. A bank active signal control part(150) generates a bank active signal in response to an external refresh active signal inputted from the outside, and enables the bank active signal only when the internal refresh active signal is enabled.
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