发明名称 AGILE DECODER
摘要 <p>A decoder arrangement (10) includes a processor (12) programmed to decode multiple streams (111-11n), including multiple streams of different formats, In terms of functionality, the decoder arrangement includes a routing stage (13) routes each streams to different decoder stages (141-14n), each capable of decoding a stream of a particular format to yield an uncompressed stream at its output. Each of plurality of buffer stages (161-16n) stores a successive frame of an uncompressed stream output by an associated decoder stage. An output stage scales and the frames stored by the buffer stages to a common size for input to a display device (22).</p>
申请公布号 KR20070105999(A) 申请公布日期 2007.10.31
申请号 KR20077018642 申请日期 2007.08.14
申请人 THOMSON LICENSING 发明人 DE LUCA MICHAEL ANTHONY
分类号 H04N7/26;H04N7/24 主分类号 H04N7/26
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