发明名称 Video coding and decoding with partial parallel processing
摘要 <p>An image data processing apparatus includes: plural arithmetic processing sections; a main memory; and a cache memory, wherein slices of the image data are sequentially and cyclically assigned to the plural arithmetic processing sections and plural slices to be processed are set as objects of processing, respectively, and the plural arithmetic processing sections process the image data in parallel to establish a consistent relationship of the processing of each slice with processing of the immediately preceding slice, in which the current slice and the immediately preceding slice can be simultaneously processed in parallel so that a reference macroblock of the macroblock in processing in the current slice may partly overlap with a reference macroblock of the macroblock in processing in the immediately preceding slice.</p>
申请公布号 EP1850598(A1) 申请公布日期 2007.10.31
申请号 EP20070251643 申请日期 2007.04.19
申请人 SONY CORPORATION 发明人 ITO, YOSHIYUKI;FUKUSHIMA, TETSUYA;YANAGITA, YUKIO
分类号 H04N19/00;H04N19/426;H04N19/436;H04N19/51;H04N19/60;H04N19/625;H04N19/91 主分类号 H04N19/00
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