| 摘要 |
PROBLEM TO BE SOLVED: To accurately receive output data by outputting data corrected according to communication circumstances or a reception side at a transmission side. SOLUTION: This interface circuit 1 is provided with a detection part 30 for detecting a specific pattern from the arrangement of output data; a shift clock generation part 120 for changing the cycle of a shift clock in response to a detection result; a shift register part 10 for changing the data output width by the shift clock, and for outputting the data as driving data; and an output part 15 of an open drain configured of an N channel transistor 15a and a pull-up resistance 15b to be driven by the driving data. The detection part 30 detects the arrangement of output data which are 0 at present, and which are 1 the next time, and a shift clock generation part 120 shortens and prolongs the cycle of the shift clock corresponding to 0 and 1. COPYRIGHT: (C)2008,JPO&INPIT
|
