Memory device with reduced stand-by mode power consumption

摘要

The present invention discloses a memory device. In one embodiment of the present invention, the memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines. At least one word line decoder is coupled to the word lines for selecting the memory cell for read or write operation. The word line decoder includes at least one last stage driver having at least one PMOS transistor and at least one NMOS transistor, the PMOS transistor having a threshold voltage substantially higher than that of the NMOS transistor, thereby reducing the power consumption of the memory device in the stand-by mode.