| 摘要 |
An integrated circuit and a manufacturing method thereof are provided to maximize a capacitor region without increasing a layout area by forming a laminated capacitor on an upper portion of a DRAM chip. An integrated circuit includes a cell array region(D) having a capacitor, and a peripheral circuit region(E) formed around the cell array region. A ferroelectric capacitor region(E) is formed on an upper layer of the cell array region and the peripheral circuit region, and has a ferroelectric capacitor device. A pump capacitor used in a pump circuit of the peripheral circuit region, a decoupling capacitor used in an output terminal of the pump circuit of the peripheral circuit region, and a decoupling capacitor used in a power terminal of the peripheral circuit region are used as the ferroelectric capacitor device.
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