发明名称 |
SEMICONDUCTOR MEMORY DEVICE IMPROVED IN DATA WRITING |
摘要 |
A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a second level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.
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申请公布号 |
US2007247912(A1) |
申请公布日期 |
2007.10.25 |
申请号 |
US20070738636 |
申请日期 |
2007.04.23 |
申请人 |
KAMIGAICHI TAKESHI;SHIROTA RIICHIRO |
发明人 |
KAMIGAICHI TAKESHI;SHIROTA RIICHIRO |
分类号 |
G11C16/04;G11C11/34 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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