Delay lock clock synthesizer and method thereof

摘要

A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.