| 摘要 |
The present invention provides methods, systems and apparatus to control instruction sequencing for a vector processor in a parallel processing environment. It enhances standard Vector Processing architectures by using two independent processing units working in conjunction to produce a highly efficient data processing ensemble. In an example embodiment, the two processors include a Scalar Processor and a separate Vector Processor. The Scalar Processor has its own Instruction Store, General Purpose Registers and Arithmetic Logic Unit. It can execute a standard instruction set including branch and jump instructions. It's function is to control the processing sequence of the Vector Processor. The Vector Processor has an independent Instruction Store, a dedicated Register along with dedicate functional elements to perform vector operations. The Vector Processor does not execute any sequencing instructions such as branch or jump but executes a serial instruction sequence starting and ending at locations determined by the Scalar Processor.
|
