发明名称 Scalable high performance non-volatile memory cells using multi-mechanism carrier transport
摘要 A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions are formed at the bottom of the trenches and the tops of the mesas formed by the trenches. An enriched region is formed in the substrate adjacent to and substantially surrounding each diffusion region in the substrate. Each enriched region has a matching conductivity type with the substrate. A gate insulator stack is formed over the substrate and each of the plurality of select gates. A word line is formed over the gate insulator stack.
申请公布号 US2007247921(A1) 申请公布日期 2007.10.25
申请号 US20070821627 申请日期 2007.06.25
申请人 MICRON TECHNOLOGY, INC. 发明人 BHATTACHARYYA ARUP
分类号 G11C16/04;H01L21/336 主分类号 G11C16/04
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