| 摘要 |
An SIMD arithmetic processing device having a processing element based on the VLIW system which is capable of simultaneously executing a plurality of instruction streams by one sequencer, which includes a PE array 109 formed of PE based on the k-way VLIW system capable of simultaneously executing instructions to the maximum of k and one sequencer CP 103 for controlling the array, the CP broadcasting an instruction selection information code X 106 other than the number k of instruction codes 104 to each PE. Each VLIW type PE includes a W-bit (W□k) mask register MR 101 , an instruction selection circuit SEL 100 for restoring the instruction codes 104 broadcast from the CP to instruction streams to the maximum of k, and an instruction selection control unit SU 102 for generating an instruction selection control signal CX 107 for controlling the instruction selection circuit SEL 100 based on the mask register MR 101 and the instruction selection information code X 106.
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