发明名称 Output buffer circuit and system including the output buffer circuit
摘要 An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from 'L' level to 'H' level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from 'H' level to 'L' level in the first time period.
申请公布号 US2007247193(A1) 申请公布日期 2007.10.25
申请号 US20070727501 申请日期 2007.03.27
申请人 KAWASAKI MICROELECTRONICS, INC. 发明人 KURAMASU TOMOAKI
分类号 H03K19/094 主分类号 H03K19/094
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