A pulse generator for a flip-flop, using a pull-down circuit with two series transistors

摘要

A CMOS flip-flop using clocked inverters (figures 9-12) is activated by narrow complementary pulses produced by a self-terminating pulse generator 300 which outputs a narrow pulse in response to the leading edge of a square input clock signal. The pulse generator comprises a CMOS delay circuit 306 in which the pull-down branch comprises two series-coupled NMOS transistors 804,806 with a common input gate signal N. The pulse generator uses few logic gates, thereby reducing power consumption and circuit area.