WRITE SCHEME OF SEMICONDUCTOR MEMORY DEVICE

摘要

A write scheme of a semiconductor memory device is provided to reduce the layout and current consumption of a semiconductor memory chip, by reducing the number of data lines by mixing a parallel register scheme and a serial register scheme together during a write operation. A sensing signal control part outputs a rising sensing signal and a falling sensing signal by buffering a data strobe signal. An input circuit part transfers data to a first input line by buffering input data. A latch part(250) latches data from the first input line and allocates the data to a first data line and a second data line in response to the rising sensing signal and the falling sensing signal. A clock buffer part outputs a strobe pulse and a shift enable signal by buffering an external clock. A control part(280) outputs a first input control signal and a second input control signal in response to the strobe pulse and the shift enable signal. A first output latch part(290a) outputs the data transferred to the first and the second data line first to a first and a second global input/output line according to the first input control signal. A second output latch part(290b) outputs the data transferred to the first and the second data line secondly to a third and a fourth global input/output line according to the second input control signal.