发明名称 Fabrication method for a damascene bit line contact plug
摘要 A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.
申请公布号 US7285377(B2) 申请公布日期 2007.10.23
申请号 US20030715616 申请日期 2003.11.18
申请人 NANYA TECHNOLOGY CORPORATION 发明人 CHEN YI-NAN;LIN JENG-PING;LIN CHIH-CHING;MAO HUI-MIN
分类号 G03F7/00;G03F7/36;H01L21/60;H01L21/768;H01L21/8239;H01L21/8242;H01L27/105 主分类号 G03F7/00
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