发明名称 Convolutional encoder and method of operation
摘要 Convolutionally encoding a data stream includes inputting a first block of two or more bits in parallel into a shift register. A number of intermediate calculations are performed in parallel using a number of respective delayed shift register outputs; and said number of intermediate calculations are output to form a convolutionally encoded sequence. In one example, a register (of individual bits stored in words), is set up. The register is longer than the constraint length means that a relatively large number of input bits can be read from memory only once, thus avoiding many independent moves of operands to and from memory. Since the register is longer than the constraint length, the register need only be shifted once for every 'a+1' input bits, rather than once for each bit.
申请公布号 US7287210(B2) 申请公布日期 2007.10.23
申请号 US20020255278 申请日期 2002.09.26
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 MACDOUGALL SCOTT
分类号 H03M13/23;H03M13/27 主分类号 H03M13/23
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