Memory device with built-in test function and method for controlling the same

摘要

A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.