| 摘要 |
A word line control circuit of a pseudo SRAM for continuous burst mode operation is provided to generate a delayed control signal which controls a word line counter considering time required for reading or writing for a repair cell when a word line is changed so as to enable reading or writing for the repair cell. A word line control circuit(100) of a pseudo SRAM for continuous burst mode operation comprises an address detection unit(110), a CAS latency delay unit(120), a word line reset signal generation unit(130), a detection signal generation unit(140), a counter control circuit(150) and a word line counter(160). The address detection unit generates an address detection signal in response to a column address signal. The CAS latency delay unit delays the address detection signal as much as CAS latency and outputs the delayed signal. The word line reset signal generation unit generates a word line reset signal having different delay time for writing or reading operation in response to the delayed signal and a writing/reading signal. The detection signal generation unit generates a detection signal in response to the word line reset signal and the detection signal. The word line counter outputs a low address signal in response to the counter control signal.
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