发明名称 CML CIRCUIT AND CLOCK DISTRIBUTION CIRCUIT USING SAME
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a technology of reducing the power consumption and a power noise in an ordinary operation state or a test state at a low speed operation and decreasing ringing of a clock waveform caused by an excessive driving force while preventing missing of a clock waveform for a prescribed first period due to the effect of a clock wiring and the RC component of a clock driver of a next stage at application of power or upon returning from a clock stop state such as a clock gating state. <P>SOLUTION: A boost circuit 12 is operated only at returning from the clock stop state. An ordinary same action buffer continues its operation while a reference signal REF is active. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2007274082(A) 申请公布日期 2007.10.18
申请号 JP20060094302 申请日期 2006.03.30
申请人 NEC CORP 发明人 IBUKA HIROSHI
分类号 H03K19/0175;G06F1/10;H03K5/15 主分类号 H03K19/0175
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