发明名称 FAILURE ANALYSIS PROGRAM, RECORDING MEDIUM WITH PROGRAM RECORDED THEREON, FAILURE ANALYSIS METHOD, AND FAILURE ANALYSIS DEVICE
摘要 PROBLEM TO BE SOLVED: To improve reliability of a semiconductor integrated circuit and shortening its manufacturing period of time. SOLUTION: Failure analysis device 1100 extracts a partial path containing a failure part from among paths in a circuit to be analyzed by a partial path extraction section 1101, then detects an expansion path from a circuit element at a front stage of a start point of the extracted partial path via the partial path to a circuit element at a rear stage of an end point of the partial path by a path detection section 1102, extracts the shortest expansion path from among a group of the expansion paths by an expansion path extraction section 1103, determines whether the path length of the expansion path is longer than a prescribed reference length by a determination section 1104, and determines the expansion path as a path to be used in failure simulation by a decision section on the basis of the decision results determined by the determination section 1104. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007271290(A) 申请公布日期 2007.10.18
申请号 JP20060093822 申请日期 2006.03.30
申请人 FUJITSU LTD 发明人 HIRAIDE TAKAHISA
分类号 G01R31/28 主分类号 G01R31/28
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