| 摘要 |
A well bias voltage generation circuit capable of controlling a well bias voltage and a method for compensating the well bias voltage are provided to reduce timing mismatch between transmission delay due to a resistor and propagation delay due to a transistor, by adjusting the well bias of the transistor, when there is timing mismatch in a circuit using a signal transferred from a transmission line and a signal transferred through the transistor. A well bias voltage detection part(100) detects the level of a well bias voltage of a number of transistors. An offset compensation part(200) provides a constant well bias voltage by compensating an offset of the transistors. An external voltage delay control part(300) generates a control signal to control the level of the well bias voltage provided from the offset compensation part according to the level variation of an external voltage by detecting the level of the external voltage. An oscillator part(400) generates a pulse signal whose period is controlled according to the state of the control signal. A pumping part(500) pumps the well bias voltage provided from the offset compensation part according to the period of the pulse signal.
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