| 摘要 |
A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.
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