METHOD OF ERASING AN EEPROM DEVICE

摘要

The present application addresses the problem arising during the erasure of EEPROMs where the FN tunnelling erase cycle is not self-limiting. Existing methods address this problem by employing monitoring algorithms. However, these algorithms slow the erase procedure time. The present application provides an alternative method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The method comprises the initial step of raising the potential at the erase gate and lowering the potential at the control gate to cause FN tunnelling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a sufficient value to cause to start FN tunnelling through the oxide of the transistor. A new structure particularly suitable for this method is also disclosed.