发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULTING FILM
摘要 A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film ( 20 ) and a silicon nitride film ( 21 ) being formed, p-type impurity ions ( 23 .sub. 1, 23 .sub. 2 ) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan<SUP>-1 </SUP>(W 2 /T)<alpha<=TAN<SUP>-1 </SUP>(W 1 /T), where W 1 is an interval between a first portion ( 21 <SUB>1</SUB>) and a fourth portion ( 21 <SUB>4</SUB>) and an interval between a third portion ( 21 <SUB>3</SUB>) and a sixth portion ( 21 <SUB>6</SUB>); W 2 is an interval between a second portion ( 21 <SUB>2</SUB>) and a fifth portion ( 21 <SUB>5</SUB>); T is a total film thickness of the silicon oxide film ( 20 ) and the silicon nitride film ( 21 ). When the implant angle alpha is controlled within that range, impurity ions ( 23 <SUB>1</SUB> , 23 <SUB>1</SUB>) are implanted into a second side surface ( 10 A<SUB>2</SUB>) and a fifth side surface ( 10 A<SUB>5</SUB>) through a silicon oxide film ( 13 ).
申请公布号 US2007243687(A1) 申请公布日期 2007.10.18
申请号 US20070767734 申请日期 2007.06.25
申请人 RENESAS TECHNOLOGY CORP. 发明人 TANAKA YOSHINORI;HORITA KATSUYUKI;KOBAYASHI HEIJI
分类号 H01L21/336;H01L21/8242;H01L21/76;H01L21/8238;H01L27/108 主分类号 H01L21/336
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