发明名称 WIRING LAYOUT APPARATUS, WIRING LAYOUT METHOD, AND WIRING LAYOUT PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 A wiring layout apparatus includes a layout design unit configured to design a wiring layout for a semiconductor integrated circuit; a critical wiring detection unit configured to analyze a delay of signal propagation in the wiring layout so as to detect wiring strip conductors that configure a signal path whose timing is critical; a rewiring unit configured to rearrange the wiring strip conductors so as to improve the uniformity of a wiring pattern of an area in the vicinity of the critical wiring strip conductor, with regard to the wiring layout; and a strip-conductor-size variation determination unit configured to evaluate the uniformity of the pattern of the rearranged wiring layout so as to determine whether or not variation in the size of the critical wiring strip conductor falls within a tolerance range.
申请公布号 US2007245286(A1) 申请公布日期 2007.10.18
申请号 US20070733940 申请日期 2007.04.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 UEDA TOSHIAKI
分类号 G06F17/50 主分类号 G06F17/50
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