| 摘要 |
PROBLEM TO BE SOLVED: To suppress variation in output voltage from a loop filter, when a PLL circuit is locked. SOLUTION: When the phase of a reference clock signal matches the phase of a feedback clock signal, an UP signal and a DOWN signal having a short on time are fed to two MOS transistors of a charge pump circuit at the falling timing of the reference clock signal and the feedback clock signal. Since the through-current of the charge pump circuit can be reduced, variations in the output voltage, from a loop filter, due to the through-current can be suppressed. COPYRIGHT: (C)2008,JPO&INPIT
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