| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten a design period and decrease power noise in a semiconductor integrated circuit and an EMI problem of a product. <P>SOLUTION: A source synchronous type interface for transmitting a clock and data at the same time is adopted for an interface between hierarchical blocks. A receiver 24 of a receiver side block 22 is provided with a clock phase detector 27 and a VDL 28 for configuring a mesochronous type synchronization circuit, receives data of the inter-block interface without setup/hold violation and transfers the data to an internal circuit of the receiver side block 22. <P>COPYRIGHT: (C)2008,JPO&INPIT |
