| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase change memory formed using a self-aligned process in which a physical memory cell size is scaled down. <P>SOLUTION: The phase change memory is provided with arrays having a plurality of transistors forming a plurality of rows and columns, first conductive lines forming a plurality of columns, while crossing the arrays, and second conductive lines forming a plurality of rows, while crossing the arrays and encapsulated by dielectric material. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory is provided with phase change elements, between the second conductive lines and contacting the first conductive lines, and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT |
