| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processor enabling high-level parallel processing by logic circuits (user logics) through simple control, in use of a plurality of integrated circuits each having a CPU and user logic, without needing synchronization (arbitration) of CPUs. SOLUTION: In the information processor in which a plurality of integrated circuits each configured so that a CPU, a user logic and a bridge are connectable through an internal bus are mutually connected through an external bus, one integrated circuit of the plurality of integrated circuits is set as a master integrated circuit for unifying the plurality of integrated circuits, and the other circuit is set as a slave integrated circuit in which the CPU is fixed to a reset state. The CPU of the master integrated circuit controls the user logic of the slave integrated circuit through the bridge and the external bus. The CPU of the master integrated circuit manages a memory address space for the user logic of the slave integrated circuit as a different memory space address. COPYRIGHT: (C)2008,JPO&INPIT
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