| 摘要 |
A programmable delay circuit includes a plurality of delay blocks, a plurality of corresponding tri-state drivers and at least one decoder. The delay blocks are connected together so as to form a series chain. Each of the tri-state drivers includes an input connected to an output of a corresponding one of the delay blocks, and a control input adapted to receive one of multiple control signals. The tri-state driver is operative in one of at least a first mode and a second mode as a function of a corresponding one of the control signals. In the first mode, an output signal generated at an output of the tri-state driver is a function of a voltage level at the input of the tri-state driver, and in the second mode the output of the tri-state driver is in a high-impedance state. The output of each of the tri-state drivers is coupled together and forms an output of the programmable delay circuit. The decoder is connected to the plurality of tri-state drivers. The decoder includes at least one control input for receiving at least a second signal and is operative to generate the control signals for activating a corresponding one of the tri-state drivers as a function of the second signal.
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