LOW POWER DETERMINISTIC BIST USING SPLIT LFSR

摘要

A low power deterministic test pattern BIST(Built-In Self Test) method using a split LFSR(Linear Feedback Shift Register) and an apparatus thereof are provided to reduce the number of shifts in a scan chain by 50% also, by using the structure capable of generating a low power test pattern when a deterministic test pattern is applied, in relation to a scan operation consuming highest power in a BIST technique. According to a deterministic test pattern BIST method of testing a semiconductor device by applying a test pattern to a scan chain of the device, a test cube generated by ATPG(Automatic Test Pattern Generation) is splitted into 0 set cube and 1 set cube(106). A test pattern is generated by assembling test patterns generated from the two test cubes. When generation values are judged to be equal by comparing the two generated test patterns(118), the generation values are used as an input value of the scan chain(120). When the generation values are not equal, a prior scan chain input value is used(122).