发明名称 Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design
摘要 A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.
申请公布号 US7284218(B1) 申请公布日期 2007.10.16
申请号 US20050084778 申请日期 2005.03.18
申请人 CALYPTO DESIGN SYSTEMS, INC. 发明人 ROY SUMIT;HASTEER GAGAN;MATHUR ANMOL
分类号 G06F17/50 主分类号 G06F17/50
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