| 摘要 |
The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
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