| 摘要 |
A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functional mode, input data bypasses the master latch and transports directly to the CBL output via the slave latch. The CBL effectively removes the master latch from the circuit in the high speed functional mode. However, in the lower speed test mode, input test data travels via both the master and slave latches to the CBL output.
|
