发明名称 High level verification of software and hardware descriptions by symbolic simulation using assume-guarantee relationships with linear arithmetic assumptions
摘要 A state-transition system is extracted from a high-level description of a design. Assumptions regarding states of the design are determined for an initial clock cycle. Linear arithmetic relations are introduced to these assumptions. Guarantees are determine that provide properties of the design that hold after a fixed number of clock cycles. Symbolic simulation is performed for a limited number of clock cycles on the state transition system of the design. If the guarantees hold once simulation is performed, the design is verified. Otherwise, counter-examples are generated.
申请公布号 US7283945(B2) 申请公布日期 2007.10.16
申请号 US20010956571 申请日期 2001.09.18
申请人 FUJITSU LIMITED 发明人 RAJAN SREERANGA P.
分类号 G06F17/50;G06F9/45;G06F11/36 主分类号 G06F17/50
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