| 摘要 |
A tri-state pulse density modulator includes a first switch device coupled to a high voltage, and a second switch device coupled to a low voltage. An adder receives a pulse density modulation (PDM) input signal and a latched input signal to generate an output sum signal and a carry signal. A latch module coupled with the adder latches the output sum signal with a clock signal to generate the latched input signal. A control circuit module responsive to the carry signal for selectively turns off the first and second switch devices to generate the PDM output signal at a tri-state voltage between the first and second voltages, or turns on the first or second switch device to generate the PDM output signal at the first or second voltage, respectively. Thus, the PDM output signal only switches between the tri-state voltage and either the first voltage or the second voltage.
|
