| 摘要 |
The present invention is a method, and resulting device, for fabricating memory cells with an extremely small area. The small area requirement is met due primarily to two significant factors. First, a judicious use of spacers allows a control gate/wordline or select line to be fabricated in extremely close proximity to an associated plurality of floating gates. Additionally, each of the plurality of floating gates is supplied with a majority carrier (e.g., electrons) through a charge injector. Each of the plurality of injector regions is made by doping a localized area (e.g., through injector ion implantation) creating a subsurface highly-doped region that is setup to receive bias from a nearby contact for charge generation, i.e., a tunneling injector.
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