METHOD AND CIRCUIT FOR REDUCING POWER CONSUMPTION IN INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce power consumption at a high-frequency disable cycle. SOLUTION: The method of this invention prevents a transient current at high-frequency disable cycle and disables DC current paths after a minimum delay time thereby reducing the power consumption. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to the transient current. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down the internal DC paths. Simultaneously, the high impedance functionality of the output drive of the chip-disable signal is preserved. COPYRIGHT: (C)2008,JPO&INPIT