Shift register with four phase clocks

摘要

A shift register comprising means for providing a first pair of clock signals, CLK 1 and XCLK 1 , with a first frequency, f₁, and a second pair of clock signals, CLK 2 and XCLK 2 , with a second frequency, f₂, where the second frequency f₂ is different from the first frequency f₁, and means for generating a plurality of signals responsive to a start pulse signal, the first pair of clock signals CLK 1 and XCLK 1 , and the second pair of clock signals CLK 2 and XCLK 2 . Each of the plurality of signals is sequentially shifted from the start pulse signal.