FIFO memory data pipelining system and method for increasing I²C bus speed

摘要

An I²C system includes an I²C bus which includes an SCK (serial clock) conductor and an SDA (serial data) conductor, a master device coupled to the SCK conductor and the SDA conductor for sending and receiving data signals and serial clock signals. The master device includes a CPU, clock generation circuitry, and a control circuit that is coupled to the CPU, the SCK conductor, the SDA conductor, and the clock generation circuitry. A FIFO memory is coupled between the CPU and the control circuit. The CPU executes an address/data instruction, after sending a stop condition and then a start condition on the I²C bus, by causing an address byte and a plurality of data bytes to be written into the FIFO memory, causing the address byte to be read from the FIFO memory and transmitted on the I²C bus, causing a next data byte to be read from the FIFO memory and transmitted on the I²C bus, and repeating reading and transmitting of the data bytes until all of them have been transmitted on the I²C bus. A stop condition then is sent on the I²C bus.