A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING USING A DELAYED INVERSION POINT TECHNIQUE

摘要

A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.