发明名称 |
DECODING CIRCUIT AND DISPLAY APPARATUS |
摘要 |
In each of sub-decoding circuits at a first stage provided for a plurality of output candidates arranged adjacently, for selecting corresponding output candidates in accordance with a bit of multibit data for transmission to subsequent stage sub-decoding circuits, unit decoders are arranged in parallel in a direction perpendicular to an arranging direction of the output candidates. A size in a vertical direction along which reference voltages of the output candidates of a decoding circuit are arranged can be reduced without increasing a size in a horizontal direction.
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申请公布号 |
US2007237407(A1) |
申请公布日期 |
2007.10.11 |
申请号 |
US20070696891 |
申请日期 |
2007.04.05 |
申请人 |
MITSUBISHI ELECTRIC CORPORATION |
发明人 |
HASHIDO RYUICHI;AGARI MASAFUMI;MURAI HIROYUKI |
分类号 |
G06K9/36 |
主分类号 |
G06K9/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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